This invention relates to the integrated circuit structure of the dummy cell of a dynamic random access memory (RAM) employing an insulated gate type field effect transistor (hereinbelow, simply termed "MISFET"). More particularly, it relates to the structure of a dummy cell for use in a one-transistor cell memory.
A dynamic RAM which employs the so-called one-transistor memory cell or one-device memory cell consisting of one MISFET and one capacitor has been well known as stated in, for example, the literature "IEEE Journal of Solid-State Circuits, Vol. SC-10, No. 5, pp. 255-261, Oct. 1975" and "Electronics, Apr. 28, 1977, pp. 115-119". The fundamental circuit of this dynamic RAM is shown in FIG. 1.
The circuit includes a memory cell CELL.sub.1 which consists of a capacitor C.sub.1 for storing an information therein and a MISFET Q.sub.1 for transferring the information; a dummy cell CELL.sub.2 which consists of a capacitor C.sub.2, a transfer MISFET Q.sub.2 and a clearing MISFET Q.sub.3 and which serves to apply a reference potential for reading out the information; and a pre-amplifier or sense amplifier PA of the flip-flop type.
FIG. 2 is an operating waveform diagram of the circuit in FIG. 1. In operation, the clearing MISFET Q.sub.3 of the dummy cell CELL.sub.2 is turned "on" by the high level of a control voltage V.sub.H, thereby to discharge charges in the capacitor C.sub.2. Thereafter, when the level of the control voltage V.sub.H has become a level (low level) which turns the MISFET Q.sub.3 "off", word signals V.sub.w1 and V.sub.w2 of high level are respectively applied to word lines W.sub.1 and W.sub.2 so as to turn "on" both the MISFETs Q.sub.1 and Q.sub.2. Thus, the level V.sub.D1 of a digit line D.sub.1 to which the memory cell CELL.sub.1 is connected is brought to a level (D.sub.H or D.sub.L) corresponding to the information "1" or "0" stored in the capacitor C.sub.1 of the memory cell, while the level V.sub.D2 of a digit line D.sub.2 to which the dummy cell CELL.sub.2 is connected is brought to the intermediate level E (reference voltage level) between the high level D.sub.H and low level D.sub.L of the digit line D.sub.1. As a result, the preamplifier PA is latched according to the levels of the digit lines D.sub.1 and D.sub.2 and delivers a certain read-out signal level of "high" or "low" to the digit line D.sub.1 or D.sub.2 because it is constructed of the flip-flop type amplifier.
In case of fabricating such dynamic RAM in the form of an integrated circuit within a single silicon substrate, the dummy cell CELL.sub.2 has heretofore been put into a structure as shown in FIG. 3.
A supply voltage V.sub.DD is applied to a gate electrode 3, to form an n-type inversion layer 6 in the surface of a p-type semiconductor substrate 1 through a gate insulating film 2. Thus, the capacitor C.sub.2 is constructed between the gate electrode 3 and the inversion layer 6. The clearing MISFET Q.sub.3 is constructed in such a manner that a gate electrode 4b for applying the clear control signal V.sub.H is formed on the surface of the semiconductor substrate 1 between the inversion layer 6 and a semiconductor region 5b connected with the ground point of the circuit. The transfer MISFET Q.sub.2 is constructed in such a manner that a gate electrode 4a for applying the singla V.sub.w2 synchronized with the word line select signal V.sub.w1 is formed on the surface of the semiconductor substrate 1 between the inversion layer 6 and a semiconductor region 5a connected with the digit line D.sub.2.
The inventor, however, has revealed that the following problem is involved in the dynamic RAM having the prior-art dummy cell structure as described above.
In the structure of FIG. 3, a channel capacitance C.sub.3 is parasitically formed between the inversion layer 6 and the gate electrode 4b, and at the transition of the potential V.sub.H of the gate electrode 4b from the high level to the low level, the clear level at one end F of the capacitor C.sub.2 changes due to the capacitive coupling of the parasitic capacitance C.sub.3. Letting V denote the transition voltage of the gate electrode 4b, the variation .DELTA.V at the end F of the capacitor C.sub.2 is obtained by the following equation: ##EQU1##
Accordingly, the quantity of charges which is delivered from the digit line D.sub.2 to the capacitor C.sub.2 when the MISFET Q.sub.2 has turned "on" at the read-out changes due to the capacitance C.sub.3. Therefore, the reference voltage level for the read-out which is given to the digit line D.sub.2 is dependent upon the capacitance C.sub.3.
On the other hand, when the dummy cell is manufactured into the form of the integrated circuit, errors of mask-alignment in the manufacturing process are unavoidable. It is therefore inevitable that, in forming the gate electrode 3 of the first layer and the gate electrodes 4a and 4b of the second layer, the surface area by which the gate electrode 4b opposes to the semiconductor substrate 1 through the gate insulating film 2 changes on account of the error of mask-alignment between masks for forming the gate electrodes of the first and second layers. For this reason, the value of the parasitic capacitance C.sub.3 deviates, and the read-out reference voltage level of the digit line D.sub.2 has a small margin for the read-out level of the high or low level.